The present invention relates generally to information processing systems and more particularly to an improved information transfer methodology in a computer related environment.
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term xe2x80x9cbandwidthxe2x80x9d is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or xe2x80x9cPCIxe2x80x9d system bridge circuit buffers are assigned to PCI devices, which are installed in PCI xe2x80x9cslotsxe2x80x9d and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted into PCI xe2x80x9cslotsxe2x80x9d, i.e. into board connector terminals mounted on a system motherboard.
In general, each PCI bus is connected to a next higher level bus in the system through a PCI bridge circuit. Each PCI bus in a system may have up to four slots (at 33 MHz) for devices or adapters connected to the PCI bus. In extensive computer systems, PCI busses are connected to other PCI busses through PCI-to-PCI bridge circuits which are, in turn, connected to one or more of the slots on higher level PCI busses. Each bridge circuit in the system includes a number of buffers which have been, in the past, assigned to corresponding ones of the PCI slots, for use in temporarily storing information transferred to and from the corresponding assigned devices installed in the PCI slots of the system. For example, in FIG. 1, a typical PCI system includes one or more CPUs 101, 105, which are connected to a system bus 103. A memory controller 107 and memory unit 109 are also connected to the system bus 103. The bus 103 is extended 111 for further system connections to other system devices and networks which are known in the art but are not specifically illustrated in order not to obfuscate the drawings and distract from the disclosure of the present invention.
The system bus 103 is also coupled through a PCI Host Bridge (PHB) circuit 113 to a first PCI bus 119. The PHB 113 is shown to include a group of buffers 117 and an arbitrator circuit 115. The first PCI bus 119 includes four devices designated xe2x80x9cS1xe2x80x9d, xe2x80x9cS2xe2x80x9d, xe2x80x9cS3xe2x80x9d and xe2x80x9cS4xe2x80x9d which are arranged for receiving PCI devices such as I/O adapter devices xe2x80x9cAxe2x80x9d 121, xe2x80x9cBxe2x80x9d 123, and xe2x80x9cCxe2x80x9d 125. The fourth device in the example is a PCI-to-PCI bridge (PPB) 127 to a second PCI bus 129. The second PCI bus is shown to be connected to three additional I/O adapter devices xe2x80x9cExe2x80x9d 131, xe2x80x9cFxe2x80x9d 133 and xe2x80x9cGxe2x80x9d 135. Each of the PCI devices on the PCI bus has separate xe2x80x9crequestxe2x80x9d (REQ) and xe2x80x9cgrantxe2x80x9d (GNT) lines to the PHB 113 as illustrated such that each PCI device may request and receive control from the arbitrator circuit 115 of the PCI bus 119 for information transfers. The devices under the PPB would request the bus through an arbiter in the PPB.
In the past, the buffers 117 were usually available for any device to utilize, and in some cases, depending on the arbiter utilized, some devices could be temporarily deprived of available buffers because each time a device is granted the bus, it could find that the buffers are full.
Thus there is a need for an improved methodology and implementing system which enables a more advantageous use of buffer availability in transferring information between devices connected within the system.
A method and implementing computer system is provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to devices on the bus based on an xe2x80x9cas neededxe2x80x9d basis for information transfers. In an exemplary PCI system embodiment, a PHB is coupled to a first PCI bus and one of the devices on the first PCI bus is a PPB which couples the first PCI bus to a second PCI bus. An initial assignment of PHB buffers in the PHB is made relative to the number of PCI adapter devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically made available and re-assigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.